At the Intel briefing, Intel's Sr VP Pat Gelsinger (pictured) set/"clarified" Nehalem's "production" date at Q4 of this year. But last November, Intel's Sr VP of the technology and manufacturing group, William Holt, told the media that Nehalem was on track to ship this Summer. Which in some instances, like with Microsoft. this could run up until early Q3 but not much beyond that!

"[This] Summer we will see Nehalem introduced which is an architecture enhancement still utilising the same feature 45-nm technology but now make substantial architectural improvement as well", said Holt.

This could also be Gelsinger trying to keep a surprise for IDF this Fall. In that case, I'm sorry to spoil the party :-)

There wasn't much news at the briefing on Nehalem:

- It's still using Intel's Core microarchitecture. A Nehalem chip will have 2 up to 8 of these core building blocks;

- 4 issue machine vs 3 for AMD;

- Hyperthreading is back and now called SMT (Simultaneous Multi-Threading). Much more efficient than adding more physical cores. Intel had to scrap SMT from the Core 2 design due to time constraint;

- A new L3 cache that will store all the data stored in the individual cores' L1 and L2 caches, thus preventing a core to go interrupt another core to fetch its memory. Now the core just goes to the L1, L2 or shared L3 caches;

- Desktop and Laptop versions will be available with on-chip integrated graphics. But it will not be based on Larabee that will not be ready by the time Nehalem ships.

And coming up, here's the video of Stephen Smith going over the Nehalem presentation. Thanks Steve for taking the time to do that personal lecture!


Finally, this is a video of the Nehalem platform demo that was done at the briefing. The system has 2 quad-core Nehalem chip for a total of 16 threads: