This morning, Intel officially launched its 6-cores chip code-named Dunnington at a press conference in San Francisco's Regis Hotel. The new Xeon 7400 processor is targeted at 4-processors servers and is the last iteration of Intel's current "front-side bus" (FSB) architecture. Dell, HP, IBM and Sun are some of the "launch" partners for Dunnington.

Inspite of some great "number crunching" performance (50% increase in some cases, Intel claims) and a 10% power efficiency improvement over a quad-core chip, Dunnington's FSB architecture still creates a bottleneck when applications need to access large chunks of memory or input-ouput interfaces like the network card, the USB/Firewire ports, etc. An issue that VP and general manager of Intel's digital enterprise division, Tom Kilroy (pictured), tried to minimise pointing to Dunnington's large 16 megabyte memory cache subsystem, ideal for virtualisation servers.

"We made great strides in improving the bandwidth in these architectures [current front-side bus server chips]... [Dunnington is ideal for] database, virtualisation, ERP, performance crunching applications... Workloads that maybe don't require as much memory period then tend to move to 2 sockets...", said Tom Kilroy.

Inspite of Intel's claims, the issues subsist as the latest 6-cores chips use the same 1066 MHz internal bus than the 4-cores ones. So the question for enterprise customers is to either wait for 8-cores Nehalem, the better designed a-la AMD next-generation Intel chip architecture - as chip analyst Nathan Brookwood suggests - , or upgrade their current quad-core systems with six-cores Dunningtons.

In the latter case, Intel is making a very attractive $2,301 proposition: buy a 12 megabyte cache 6-cores chip (Xeon E7450) for the price of a 8 megabyte quad-core one (Xeon X7350)! Hard to beat that if you're already an Intel "shop" and have standardised on the latest Intel server platform (Caneland).

Intel latest price list as of Sept 14th, 2008.

Here are Tom Kilroy's comments on Intel's server architecture limitations: